1. Technical Field
The present invention relates to the fabrication of semiconductor devices in high band gap materials such as silicon carbide, and more particularly to the fabrication of vertical-sidewall dual-mesa static induction transistors.
2. Discussion of Related Art
Silicon carbide (SiC) Static Induction Transistors (SITs) have been developed for high power radio frequency (RF) applications such as Radar, Avionics and TV Transmission. Such devices are described in U.S. Pat. Nos. 5,705,830 and 5,903,020. The conventional devices have been limited in frequency range thus far to high frequency (HF) in the range of 100-200 MHz and ultrahigh frequency (UHF) in the range of 400-500 MHz for the various applications due to excessive power gain roll-off at frequencies above 500 MHz.
There are many important applications for Radar and Avionics RF power transistors in L-Band (1.0-1.5 GHz) for which the conventional devices can not address. Consequently, high power L-Band Radar/Avionics systems are forced to use existing silicon bipolar devices that have much lower power densities, require lower operating voltages, and have significant temperature limitations.
It would therefore be desirable to use SiC SIT devices that operate at significantly higher voltages, power densities, and junction temperatures than existing silicon devices in L-Band systems. Performance advantages of SiC devices over silicon devices are made possible by the fundamental material properties of SiC. For instance, higher voltage operation with lower on-resistance arises from the 10× higher breakdown field strength of SiC compared to silicon. Higher junction temperature operation arises from the much larger bandgap (3.26 eV for 4H SiC, compared to 1.1 eV for silicon). Nevertheless, conventional SiC devices suffer from various inefficiencies.
U.S. Pat. No. 5,705,830 describes a conventional SiC SIT having a vertical conducting channel that uses Schottky barrier gate control. The source contact is on a narrow top mesa, the drain contact is on the back of the die, and the Schottky gate contact is formed on the sidewalls of a channel mesa. The requirement of making Schottky contact to the channel mesa vertical sidewalls imposes severe manufacturing difficulties, which are overcome only by use of several layers of e-beam lithography and precise angled metal evaporation and lift-off. Consequently the manufacture of such devices requires very expensive equipment and considerable engineering supervision. In addition, the Schottky gate has poor breakdown and reverse leakage characteristics resulting in reliability problems that are difficult to overcome.
An improvement over the Schottky gated SIT is described in U.S. Pat. No. 5,903,020. In the '020 patent, a single-mesa is used and the Schottky barrier gate is replaced by a junction gate. The junction gate is formed by implanting acceptor impurities, typically aluminum (Al), into the gate region using the channel mesa, with oxide sidewall spacers as the implant mask. Hence, the p-type gate is self-aligned to the n-type vertical channel. This is simpler to manufacture using conventional optical stepper lithography, and no metal contacts need to be made to the sidewall of the channel mesa.
In addition, the junction gate of the '020 patent has a larger barrier height (˜3.0 eV compared to ˜1.4 eV for the Schottky gate), which enables wider channel mesas to be formed for the same channel pinch-off voltage, VP. Because of the larger barrier height, the junction gate has a higher gate turn-on voltage (˜2.5 V) than the Schottky gate (˜1.0 V), which provides substantially higher maximum channel current (and hence, power) capability. Moreover, the junction gate has higher breakdown voltage and lower reverse bias gate leakage, making a more robust and reliable device.
As a result, the single-mesa implanted junction-gated SIT provides a robust RF power transistor for applications through UHF band. Indeed, these devices have produced the highest power UHF transistors available to date.
FIG. 1 shows an SEM image of a cross section of the conventional single-mesa implanted SiC SIT for UHF power transistors. The p-type (implanted) regions 101 show up as lighter regions in these SEM images. The source contacts are on top of the single-mesa as indicated by 107 in FIG. 1, and the drain contact is on the back of the chip (not shown). Hence, the single-mesa structure forms both the source contact and the vertical transistor channel, and current flow is modulated by voltage applied to the gate and drain contacts.
Several frequency-limiting factors are inherent to the conventional single-mesa topology. The gate junction is formed by implantation directed normally to the wafer surface at high energy. Consequently, and as shown in FIG. 1, the gate perimeter is defined by the lateral and side straggle of the highest energy implant and the resulting channel has a trapezoidal shape, as shown in Region A. An ideal channel would be of constant width throughout the length of the channel. The channel widening from the source to drain end shown in FIG. 1 reduces the gate control of channel current, which is particularly detrimental to high frequency performance. In addition, the extended perimeter of the gate junction in Region B of FIG. 1 contributes excess parasitic gate capacitance (Cgg) that further reduces the high frequency capability.